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Type: R & D Name: FPGA development engineer
Number: 2 Sex: Unlimited
Education: Junior college and above Working area: Shenzhen
Resume language: Chinese,English Work Department: R&D
Working time: Undefined Release date: 2016-12-18
Deadline: 2018-12-02
Job description:

Post responsibilities
(1) He is responsible for attending chip model selection and appraisal on hardware and software resources, performance and development tool;
(2) He is responsible for attending whole-process chip designing and all or part process from demand definition to joint debugging;
(3) He is responsible for FPGA logic, algorithm design, development, optimization, functional simulation, time sequence simulation and so forth;


Job requirements:
(1)Over three years of working experience for Bachelor’s degree or over one year of working experience for Master’s Degree;
(2) Profound understanding of FPGA device structure;
(3) Familiar with chip development surrounding and simulation debugging tools in Altera/Xinlinx/Lattice and other countries;
(4) Familiar with and mastery on FPGA development methods, designing flow and designing instruments; those with working experience on SOC designing are preferred;
(5) Versed at Verilog, HDL language and temporal constraint, time sequence analysis and time sequence optimization methods.
Please send your resume to: xiaowanang@dputech.com
 

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